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Secure AES Coprocessor

Purpose

The Secure AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture (SPA, DPA[1] and fault hardened).

Features

▪ decryption and encryption;
▪ key expander included;
▪ 128-bit data blocks;
▪ 128, 196 and 256-bit keys;
▪ supported modes: ECB, CBC, CFB, OFB, CTR, XTS, GCM, EAX and CCM;
▪ configurable architecture:
− encryption and decryption; encryption only; decryption only;
− hardware datapath size: 32, 64 or 128-bits;
− optional fault-injection countermeasures;
− optional DMA support.
▪ high performances:
− 11 cycles for the fastest architecture;
− 19 kgates for the smallest architecture;
− more than 1 GHz in a 65 nm LVT process.
▪ state-of-the-art countermeasures against SPA, DPA[1] and fault injection attacks;
▪ AMBA APB bus interface (AHB with the optional DMA);
▪ C low-level API.

Deliverables

▪ VHDL source codes;
▪ C non-regression tests;
▪ C low-level API;
▪ code coverage, linker and synthesis reports;
▪ design specification.

[1] Third-party fees apply. Please contact salesinvia.fr for any further information.

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