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Power Manager

Purpose

The Power Manager is a fully-integrated Low-DropOut (LDO) voltage regulator intended to power secure System-on-Chip (SoC) platforms.

Features

▪ fully-integrated LDO voltage regulator;
▪ voltage monitors supervising both the external and internal supply voltages:
− adjustable voltage detection thresholds;
− supply noise rejection through hysteresis margin.
▪ robust Power-On Reset (POR) generator;
▪ robust power-up, power-down and standby sequences;
▪ operating junction temperature range: -25°C to 105°C;
▪ regulated voltage accuracy better than ±10% through trimming;
▪ typical characteristics of a 55 nm CMOS implementation:
− worst Power Supply Rejection Rate (PSRR) higher than 35 dB (w/o external decoupling capacitor);
− startup time shorter than 100 µs;
− operating quiescent current smaller than 60 µA for a 20 mA output current;
− silicon area smaller than 0.2 mm² for a 20 mA capability.
▪ proven track record through mass production in 130 nm and 55 nm CMOS processes;
▪ silicon proven in 130 nm, 65 nm and 55 nm CMOS processes.

Deliverables

▪ GDSII stream and layer map file;
▪ Library Exchange Format (LEF) file;
▪ Circuit Description Language (CDL) netlist;
▪ Liberty Timing File (.lib);
▪ VHDL behavioral model;
▪ design specification.

Please contact salesinvia.fr for any further information.

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