The Secure Clock Generator is a fully integrated mixed-signal IP securing the clocked system against side-channel attacks.
▪ fully integrated secure clock generator;
▪ programmable frequency range (customized on request);
▪ frequency accuracy better than ±10% through trimming process;
▪ frequency monitor protecting against fault injection attacks;
▪ jittered clock option protecting against side-channel attacks;
▪ secondary clock signal generated by on-the-fly period masking;
▪ robust power-up, power-down and standby sequences avoiding clock glitches;
▪ operating junction temperature range: -40°C to 125°C;
▪ characteristics of a 55 nm CMOS implementation:
▪ − power supply voltage range: 1.2 V ±10%;
▪ − typical wake-up time shorter than 20 µs;
▪ − typical operating current consumption lower than 120 µA at 120 MHz;
▪ − silicon area smaller than 0.045 mm².
▪ proven track record through mass production in 130 nm and 55 nm CMOS processes;
▪ silicon proven in 130 nm, 65 nm and 55 nm CMOS processes.
▪ GDSII stream and layer map file;
▪ Library Exchange Format (LEF) file;
▪ Circuit Description Language (CDL) netlist;
▪ Liberty Timing File (.lib);
▪ VHDL behavioral model;
▪ design specification.