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LVDS Transceiver

Purpose

The LVDS Transceiver is a fully integrated Low-Voltage Differential Signaling (LVDS) Analog Front End (AFE) including one flow-through driver and two flow-through receivers.

Features

▪ fully-integrated Low Voltage Differential Signaling (LDVS) transceiver;
▪ two flow-through LVDS receivers;
▪ one flow-through LVDS driver;
▪ upstream and downstream bit rates up to 500 Mbit/s;
▪ straightforward output stream synchronization through an external sampling clock;
▪ power-supply voltage range:
− core side: nominal core supply voltage ±10%;
− I/O side: nominal I/O supply voltage ±10%.
▪ characteristics of a 90 nm CMOS implementation:
− core side supply voltage: 1.2 V ±10%;
− I/O side supply voltage: 1.8 V ±10%;
− operating current: 4 mA per receiver and 8 mA per driver (500 Mbit/s; Cload=10 pF);
− standby supply current lower than 250 µA;
− silicon area smaller than 0.32 mm².
▪ silicon proven in a 90 nm CMOS process.

Deliverables

▪ GDSII stream and layer map file;
▪ Library Exchange Format (LEF) file;
▪ Circuit Description Language (CDL) netlist;
▪ Liberty Timing File (.lib);
▪ VHDL behavioral model;
▪ design specification.

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