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USB Clock Recovery


The USB Clock Recovery is a fully integrated mixed-signal IP extracting the USB clock signal from the incoming USB data stream without any external component.


▪ fully integrated mixed-signal solution; no external component (no quartz, no resonator);
▪ analog transceiver fully compliant with the USB 2.0 Full-Speed specification:
− upstream data rate accuracy compliant with Table 7-9 of USB 2.0 specification (±0.25%);
− source jitter total including frequency tolerance to next transition (TDJ1) < 3.5 ns;
− source jitter total including frequency tolerance for paired transitions (TDJ2) < 4.0 ns;
− sampling method tolerant to rebounds, ±¼ bit jitter and shortened start-of-frame.
▪ on-the-fly time base unit calibration through received standard pattern synchronization;
▪ single-ended mode detection;
▪ suspend mode triggering from USB controller;
▪ resume time shorter than 2 ms;
▪ output clock signal for external DPLL;
▪ operating junction temperature range: -20°C to 105°C;
▪ gate count of the digital controller smaller than 10 kgates;
▪ characteristics of a 90 nm CMOS implementation:
− operating consumption lower than 20 mA (clock recovery and transceiver both running);
− suspended current consumption smaller than 500 µA;
− silicon area of the analog front end smaller than 0.8 mm².
▪ straightforward integration through a standard interface (customized on request).


▪ analog front end:
− GDSII stream and layer map file;
− Library Exchange Format (LEF) file;
− Circuit Description Language (CDL) netlist;
− VHDL behavioral model and Liberty Timing File (.lib).
▪ digital controller:
− VHDL source codes and testbenches
− standalone simulation patterns;
− Synopsys synthesis scripts.
▪ design specification.

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